1. Field of the Invention
The present invention relates to a nonvolatile variable resistive element including a first electrode, a second electrode, and a layer serving as a variable resistor formed of a metal oxide and sandwiched between the above electrodes, and a nonvolatile semiconductor memory device using the variable resistive element for storing information.
2. Description of the Related Art
Recently, as a high-speed operable next-generation nonvolatile random access memory (NVRAM) to replace a flash memory, various device structures such as FeRAM (Ferroelectric RAM), MRAM (Magnetic RAM), and PRAM (Phase Change RAM) have been proposed, and they face intense development competition with a view to improving performance, increasing reliability, lowering cost, and ensuring consistency with processes.
With respect to these existing techniques, RRAM (Resistive Random Access Memory) which is a nonvolatile resistive memory using a variable resistive element whose electric resistance is changed reversibly by applying a voltage pulse has been proposed. FIG. 12 shows this configuration.
As shown in FIG. 12, a conventional variable resistive element has a structure in which a lower electrode 103, a variable resistor 102, and an upper electrode 101 are laminated in this order, and it is characterized in that when a voltage pulse is applied between the upper electrode 101 and the lower electrode 103, its resistance value can be reversibly changed. A new nonvolatile semiconductor memory device can be realized by reading a resistance value which is changed by this reversible resistance changing action (hereinafter, referred to as the “switching action”).
The nonvolatile semiconductor memory device is composed by forming a memory cell array in which memory cells each including a variable resistive element are arranged in a shape of matrix in a row direction and a column direction, and by arranging periphery circuits to control programming, erasing, and reading actions of data for each memory cell of the memory cell array. Thus, as for the memory cell, there are a memory cell in which one memory cell includes one selection transistor T and one variable resistive element R (referred to as the “1T1R type”) and a memory cell in which one memory cell only includes one variable resistive element R (referred to as the “1R type”), depending on a difference in composed component. Among them, FIG. 13 shows a configuration example of the 1T1R type memory cell.
FIG. 13 is an equivalent circuit diagram showing one configuration example of the memory cell array having the 1T1R type memory cells. A gate of the selection transistor T in each memory cell is connected to a word line (WL1 to WLn), and a source of the selection transistor Tin each memory cell is connected to a source line (SL1 to SLn) (n is a natural number). In addition, one electrode of the variable resistive element R in each memory cell is connected to a drain of the selection transistor T, and the other electrode of the variable resistive element R is connected to the bit line (BL1 to BLm) (m is a natural number). In addition, the word lines WL1 to WLn are connected to a word line decoder 106, and the source lines SL1 to SLn are connected to a source line decoder 107, and the bit lines BL1 to BLm are connected to a bit line decoder 105. Thus, in response to an address input (not shown), the specific bit line, word line, and source line are selected for programming, erasing, and reading actions for the specific memory cell in a memory cell array 104.
Thus, according to the configuration in which the selection transistor T and the variable resistive element R are arranged in series, the transistor of the memory cell selected by a potential change of the word line is turned on, and programming or erasing can be selectively performed only for the variable resistive element R of the memory cell selected by a potential change of the bit line.
FIG. 14 is an equivalent circuit diagram showing one configuration example of the 1R type memory cell. Each memory cell includes the variable resistive element R only, and one electrode of the variable resistive element R is connected to the word line (WL1 to WLn), and the other electrode thereof is connected to the bit line (BL1 to BLm). In addition, the word lines WL1 to WLn are connected to the word line decoder 106, and the bit lines BL1 to BLm are connected to the bit line decoder 105. Thus, in response to the address input (not shown), the specific bit line, and word line are selected for programming, erasing, and reading actions for the specific memory cell in a memory cell array 108.
As for the above variable resistive element R, a method for reversibly changing electric resistance by applying a voltage pulse to a perovskite material known for a supergiant magnetoresistance effect, as the variable resistance material used in the variable resistor is disclosed in U.S. Pat. No. 6,204,139 (hereinafter, referred to as the “well-known document 1”) by Shangquing Liu or Alex Ignatiev at Houston University in the United States, and in “Electric-pulse-induced reversible Resistance change effect in magnetoresistive films”, Applied Physics Letter, Vol. 76, pp. 2749-2751, in 2000 by Liu, S. Q. et al. By this method, the several-digit resistance change appears in room temperature without applying an magnetic field even when the perovskite material known for the supergiant magnetoresistance effect is used. In addition, according to an element structure illustrated in the well-known document 1, as the material of the variable resistor, praseodymium calcium manganese oxide Pr1-xCaxMnO3 (PCMO) film which is a perovskite type oxide is used.
In addition, as another variable resistor material, an oxide of a transition metal element such as a titanium oxide (TiO2) film, nickel oxide (NiO) film, zinc oxide (ZnO) film, or niobium oxide (Nb2O5) film shows the reversible resistance change as shown in “Bistable Switching in Electroformed Metal-Insulator-Metal Devices”, Phys. Stat. Sol. (a), vol. 108, pp. 11-65, in 1988 by H. Pagnia et al., and in “Highly Scalable Non-volatile Resistive Memory using Simple Binary Oxide Driven by Asymmetric Unipolar Voltage Pulses”, IEDM 04, pp. 587-590, in 2004 by Baek, I. G. et al (hereinafter referred to as the “well-known document 2”).
In addition, the above-described variable resistive element shows an n-type or p-type conductivity of a semiconductor because an impurity level is formed in a bandgap by an oxygen defect in the metal oxide. In addition, it is confirmed that the resistance change is a state change in the vicinity of an electrode interface.
As for the variable resistive element using the transition metal oxide for the variable resistor, it is necessary to perform a soft breakdown process, referred to as a forming process to enable resistance switching to be realized. A voltage (forming voltage) required for the soft breakdown process is higher than a programming voltage for recording information. Meanwhile, since it is necessary to drive the variable resistive element with a fine transistor in realizing a highly integrated nonvolatile memory, the forming voltage has to be lowered.
Here, it is known that the forming voltage is roughly proportional to a film thickness of the metal oxide used for the variable resistor, and a method for lowering the forming voltage most easily is to thin the film thickness of the metal oxide as disclosed in the well-known document 2.
However, when the film thickness of the metal oxide becomes thin, a variation in characteristics could be generated due to slight fluctuation of a film forming process or surface roughness of a base substrate.